1. Field of the Invention
The present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor and a manufacturing method thereof. More particularly, the present invention relates to a CMOS image sensor, with an insulation layer of a high dielectric constant, having a non-silicided source/drain region in a pixel region and a silicided source/drain region in a peripheral circuit region, and a manufacturing method thereof.
2. Description of the Related Art
In a CMOS image sensor having a pixel region and a peripheral circuit region, a silicide layer is usually formed on a source/drain region of a MOS transistor only in the peripheral circuit region but not in the pixel region. This is because a dark current, one of the undesirable characteristics of a CMOS image sensor, can be decreased by forming a non-silicided source/drain region in the pixel region, and high performance of input/output logic in a CMOS image sensor can be achieved by forming a silicided source/drain region in the peripheral circuit region.
FIG. 1 is a cross-sectional view showing a manufacturing method of a conventional CMOS image sensor.
Referring to FIG. 1, a trench isolation layer 102 defining an active region is formed on a semiconductor substrate 100 having a pixel region and a peripheral circuit region. After forming well regions (not shown) in the pixel region and the peripheral circuit region, a gate insulation layer 104 and a gate electrode layer 106 are formed on the semiconductor substrate 100. Subsequently, an extended source/drain region 108 is formed by an ion implantation process. A gate spacer layer 110 is then formed on the sidewall of the gate insulating layer 104 and the gate electrode layer 106. A deep source/drain region 112 is then formed by another ion implantation process.
After coating an organic material layer (not shown) on the entire surface of the semiconductor substrate 100, an upper surface of the gate electrode layer 106 is exposed by an etch-back process. A mask layer pattern (not shown) is formed to cover the pixel region and to expose the peripheral circuit region by removing the organic material layer in the peripheral circuit region. Subsequently, the mask layer pattern is removed. Using a conventional typical silicidation process, a silicide layer 114 is then formed on the gate electrode layer 106 in the pixel region, and on the gate electrode layer 106 and the source/drain region 112 in the peripheral circuit region. Accordingly, a silicide layer 114 on the gate electrode layer 106 is formed in both the pixel region and the peripheral circuit region, but a silicide layer 114 on the source/drain region 112 is formed only in the peripheral circuit region.
In the conventional manufacturing method of a CMOS image sensor, however, it is difficult to use an insulating layer with a high dielectric constant as the gate insulation layer. Furthermore, an insulating layer with a high dielectric constant is thermally unstable. Therefore, even if an insulating layer with a high dielectric constant is formed as a gate insulation layer, the insulating layer with a high dielectric constant is deteriorated by a high temperature process for subsequently forming a source/drain region.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.